Focused ion beam (FIB) tools are commonly used in micro- and nano-scale additive and subtractive processing. FIBs find extensive use in micro- and nano-machining of micro-electromechanical systems (MEMS), materials science characterization and study, biology, semiconductor processing failure analysis, etc.
In applications relating to integrated circuit modification, FIB tools are commonly used to etch and deposit both conductive and insulating material. Theorized circuit corrections are often implemented by FIBs and their performance verified in a design stage prior to adjusting photomasks and altering large-scale production designs. With the development of flip-chip bonded devices and integrated circuits that include many levels of front-side metallization, circuit modification operations have begun to include back-side silicon processing, where an integrated circuit modification is implemented by etching the bulk substrate, generally silicon, using a FIB. Remaining surface thickness (RST) is an important parameter in performing back-side silicon integrated circuit modification. If too much of the silicon substrate is etched during FIB processing, circuitry on one or more transistor or device layers can be unintentionally damaged, rendering the electronics of the integrated circuit non-functional.
Conventional back-side FIB processing systems typically make use of subjective estimation of RST by an operator based on focus distance between an artifact found in the processed silicon surface and the underlying circuitry. Poor optical resolution of the artifact and a skill level of the FIB operator can reduce accuracy of this estimation. Other methods of estimating RST include removing the circuit being processed from the FIB processing device and performing ex-situ measurements of the RST. However, removing an integrated circuit from a vacuum chamber of a FIB tool to measure RST is time-consuming and introduces the possibility of circuit damage during handling. In-situ measurement can be accomplished by way of a pilot hole technique wherein a pilot hole is etched and its depth measured using the FIB. The pilot hole is etched using the FIB to remove all silicon in an area deemed to be benign to affecting operation of the circuit. In many cases, though, such an area is unavailable due to the possibility of damage to components of the circuit as a result of etching the pilot hole. In other cases, the pilot hole is too far away from an area of interest to provide an accurate measurement of the RST.